Understanding 2D Semiconductors and Their Potential

Two-dimensional (2D) semiconductors represent a paradigm shift in materials science, consisting of atomically thin layers—often just one or a few atoms thick—that exhibit exceptional electronic properties. Unlike traditional three-dimensional (3D) silicon, which faces physical limits as transistors shrink below 2 nanometers, 2D materials like molybdenum disulfide (MoS2) offer tunable bandgaps, high carrier mobilities, and superior electrostatic control. These characteristics make them ideal for next-generation electronics, including ultra-low-power devices, flexible displays, and quantum computing components.

Chinese universities have emerged as global leaders in this field, driving innovations that bridge laboratory discoveries to industrial scalability. Their work addresses longstanding challenges in producing large-area, defect-free 2D films, positioning China at the forefront of post-silicon computing.

The oxy-MOCVD Technique: A Scalability Revolution

Researchers from Nanjing University and Southeast University in Nanjing have pioneered oxygen-assisted metal-organic chemical vapor deposition (oxy-MOCVD), a technique that dramatically accelerates the growth of high-quality MoS2 films. Traditional metal-organic chemical vapor deposition (MOCVD) for MoS2 is kinetically limited, resulting in small domains (nanometer-scale) and carbon impurities from precursors. Oxy-MOCVD introduces oxygen to convert precursors into pure transition-metal oxides and chalcogens, yielding aligned domains with growth rates over 100 times faster.

On miscut sapphire substrates, this method produces uniform 150-millimeter (6-inch) single-crystal MoS2 wafers—the largest reported to date. Field-effect transistors (FETs) fabricated from these wafers achieve electron mobilities exceeding 100 cm²/V·s, free of carbon defects, enabling high-yield production akin to silicon wafers.

Performance Metrics and Device Fabrication

The transistors demonstrate 10 times higher electron mobility than those from conventional MoS2, with excellent uniformity across the wafer. This breakthrough supports Moore's Law extension by allowing higher transistor densities and faster market entry for chipmakers. Key metrics include subthreshold swings below 70 mV/dec and on-off ratios surpassing 10^6, critical for low-power logic circuits.

Integration into devices is seamless: the sapphire-hosted MoS2 transfers well to silicon, paving the way for hybrid 2D-silicon chips. Early prototypes show potential in high-frequency applications, where 2D materials outperform FinFETs and gate-all-around (GAA) silicon structures.

Peking University's InSe Wafers: Outpacing Silicon Projections

At Peking University (PKU), Professor Liu Kaihui's team developed a solid-liquid-solid growth for wafer-scale indium selenide (InSe) films on 2-inch sapphire substrates. Using magnetron sputtering followed by indium encapsulation and annealing at 550°C, they achieve single-phase crystalline films with mobilities up to 287 cm²/V·s and subthreshold swings of 67 mV/dec.

These InSe transistors exceed 2037 International Roadmap for Devices and Systems (IRDS) projections for silicon in delay and energy-delay product, with minimal drain-induced barrier lowering (DIBL) and ballistic transport at sub-10 nm scales. Published in Science, this work highlights PKU's role in validating 2D superiority.

Fudan University's 2D Innovations: From Flash to Radiation Tolerance

Fudan University researchers have created the world's first full-featured 2D flash chip, integrating MoS2 with silicon circuitry for ultra-fast memory. Their "PoX" prototype sets access speed records, while radiation-tolerant 2D systems—leveraging atomic thinness to minimize radiation damage—promise space electronics revolutions. These advancements stem from years of 2D device optimization since 2018.

The "Wuji" 32-bit RISC-V processor, a few atoms thick, outperforms silicon in speed and efficiency by 40%, underscoring Fudan's push toward commercial 2D computing.

USTC's van der Waals Integration for High-Yield Arrays

The University of Science and Technology of China (USTC) excels in device integration. Prof. Zeng Hualing's team devised an all-stacking method for wafer-scale 2D FET arrays using van der Waals (vdW) contacts. Avoiding damaging metal deposition, they achieve sharp interfaces, reducing off-state current by 95%, subthreshold swing by 50%, and on-off ratios over 10^6 in 98.4% yield MoS2 arrays.

Published in Nature Communications, this technique enables low-power ICs, vital for scaling 2D tech.

China's National Strategy and University Ecosystem

China's 14th Five-Year Plan emphasizes semiconductor self-reliance, funneling billions into university research. Institutions like Tsinghua, Fudan, PKU, Nanjing U, Southeast U, and USTC receive National Natural Science Foundation (NSFC) grants, fostering collaborations with institutes like Suzhou Nano Research Lab. This ecosystem has yielded over 50 high-impact 2D papers in 2025-2026 alone, per Nature Index.

Government initiatives like the Big Fund boost tech transfer, with universities patenting oxy-MOCVD variants and 2D FPGAs—the first wafer-scale ones integrating 4,000 transistors.

Implications for Global Electronics and Moore's Law

Wafer-scale 2D production slashes costs, enabling flexible, low-power devices for AI, 6G, and IoT. 2D chips consume 10x less energy than silicon at similar speeds, critical amid data center power crises. China's advances challenge US dominance, prompting collaborations like US-China 2D material exchanges.

For more on the seminal oxy-MOCVD paper, see the full study in Science.

Boosting Research Careers in Chinese Higher Education

These breakthroughs spur demand for PhD/postdocs in materials engineering, nanofabrication, and device physics. Universities like Nanjing U advertise 100+ research positions annually, with salaries 20-30% above average via talent programs like Thousand Talents. International collaborations offer mobility, while domestic funding hits RMB 780 billion in R&D (2026 est.).

Students benefit from state labs, with enrollment in semiconductor majors up 50% since 2023.

Challenges and Future Directions

Despite progress, challenges persist: defect control at 300mm scales, doping uniformity, and thermal management. Universities target 12-inch wafers by 2028 via hybrid oxy-MOCVD/MBE. Quantum 2D devices and neuromorphic chips loom large, with Fudan/PKU leading prototypes.

Global Perspectives and Collaborative Opportunities

Western firms eye partnerships; Samsung/TSMC explore 2D integration. Chinese universities host international workshops, fostering exchanges. For researchers, this era offers unprecedented opportunities in China's vibrant higher ed landscape.

Conclusion: China's Universities Shaping Tomorrow's Tech

From oxy-MOCVD wafers to integrated chips, Chinese institutions are redefining semiconductors. Their innovations promise efficient, scalable electronics, underscoring higher education's pivotal role in national innovation.

Photo by Jorick Jing on Unsplash