Breakthrough in Nanoscale Electronics from Peking University
The field of semiconductor technology has reached a pivotal moment with the announcement of the world's smallest ferroelectric transistor, developed by a team at Peking University. Published in the prestigious journal Science Advances, this innovation features a mere 1-nanometer gate length and operates at an ultralow voltage of 0.6 volts, setting new benchmarks for energy efficiency and scalability. Led by senior researcher Qiu Chenguang and in collaboration with Peng Lianmao from the Chinese Academy of Sciences, the device addresses longstanding barriers in integrating nonvolatile memory with logic circuits, promising transformative impacts on artificial intelligence hardware.
This ferroelectric field-effect transistor (FeFET), a type of nonvolatile memory where data is stored via the polarization states of a ferroelectric material rather than charge, traditionally suffered from high operating voltages mismatched with modern logic transistors running below 0.7 volts. The Peking University team's nanogate design circumvents this, enabling seamless monolithic integration essential for next-generation chips.
Understanding Ferroelectric Field-Effect Transistors
Ferroelectric field-effect transistors (FeFETs) leverage the unique property of ferroelectric materials, which exhibit spontaneous electric polarization that can be reversed by an external electric field. This bistable polarization—representing binary '0' and '1' states—allows for nonvolatile storage, meaning data persists without power, unlike dynamic random-access memory (DRAM).
In a typical FeFET structure, often configured as metal-ferroelectric-metal-insulator-semiconductor (MFMIS), the ferroelectric layer modulates the channel conductivity. Common ferroelectrics include hafnium zirconium oxide (HZO) or two-dimensional (2D) materials like CuInP2S6 (CIPS) used here. The challenge lies in scaling: as gates shrink below 10 nm, short-channel effects degrade performance, and coercive voltages (minimum to switch polarization) remain high, around 1-1.5 V, necessitating inefficient charge pumps.
Peking University's solution employs metallic single-walled carbon nanotubes (m-SWCNTs) as 1-nm-diameter gate electrodes, creating a 'nanogate' that concentrates electric fields and boosts capacitance coupling between ferroelectric and semiconductor layers.
The Nanogate Design: Engineering at Atomic Precision
The core innovation is the nanogate: a 1-nm m-SWCNT tip focuses the electric field, achieving enhancement factors up to 2.6 times conventional designs. This localizes the field within the 2D CIPS ferroelectric layer (thickness 6.5-70 nm), exceeding the coercive field (~1 V/nm) at applied voltages as low as 0.6 V.
Device fabrication involves chemical vapor deposition-grown SWCNTs, patterned via electron-beam lithography, stacked with multilayer graphene floating gate, h-BN dielectric, and MoS2 channel in a van der Waals heterostructure. Transmission electron microscopy confirms atomic-scale precision, with no short-channel effects due to field confinement.
- Electric field peaks at 2.7 × 106 V/cm under the nanotip.
- Capacitance ratio CFe/CMOS minimized for >100% voltage efficiency.
- Compatible with industrial processes for HfO2 or AlScN ferroelectrics.
Simulations using TCAD and Landau-Ginzburg-Devonshire theory validate the mechanism, showing Gibbs free energy minima favoring polarization switching.
Performance Benchmarks and Superior Metrics
The nanogate FeFET achieves a record current on/off ratio of 2 × 106, memory window up to 2.8 V, and programming speeds of 1.6 ns at 3 V pulses or 20 ns at 0.6 V. Switching energy is a mere 0.45 fJ/μm—about one-tenth of prior benchmarks—ideal for dense arrays.
| Metric | PKU Nanogate FeFET | Prior State-of-Art |
|---|---|---|
| Gate Length | 1 nm | ~10 nm |
| Op. Voltage | 0.6 V | >1.5 V |
| On/Off Ratio | 2×106 | ~105 |
| Speed | 1.6 ns | ~10 ns |
| Endurance | >104 cycles | ~103-104 |
| Retention | >104 s | >103 s |
Endurance exceeds 10,000 cycles with minimal degradation, retention >104 seconds at >103 on/off. Thicker CIPS yields larger windows, scalable for applications.
Read the full Science Advances paperRevolutionizing AI Chips and Neuromorphic Systems
In AI accelerators, data movement between memory and processors consumes 60-90% of energy. FeFETs enable in-memory computing, where synaptic weights are stored nonvolatily, mimicking neurons for neuromorphic hardware. This PKU transistor's low voltage eliminates charge pumps, slashing latency and power for edge AI, wearables, and IoT.
Qiu notes: “The in-memory computing capability of FeFETs aligns closely with the future evolution of AI chips,” positioning it for large model inference and brain-like processing. Benchmarks show superiority over HZO or AlScN FeFETs in voltage, speed, and energy.
- Reduces AI data center power by integrating compute-memory.
- Supports sub-1-nm nodes, defying Moore's Law limits.
- Enables dense arrays for vector-matrix multiplication in neural nets.
Link to research jobs in semiconductors at Peking University and beyond.
Peking University's Leadership in Semiconductor Innovation
Peking University (PKU), a top Chinese institution, drives China's semiconductor self-reliance amid global tensions. The School of Electronics Engineering, home to this work, benefits from National Natural Science Foundation funding. Patents filed by PKU inventors secure IP, fostering commercialization.
PKU's focus on 2D materials and van der Waals heterostructures positions it as a hub for next-gen devices. Collaborations with CAS amplify impact, aligning with China's 'Made in China 2025' for advanced chips. Explore higher education opportunities in China or research positions.
Overcoming Historical Scaling Barriers
Prior FeFETs stalled at 22-nm nodes due to depolarization fields and interface traps in HfO2. 2D ferroelectrics like CIPS offered promise but high voltages persisted. The nanogate's field concentration—verified by FTJ experiments—breaks this, with voltage efficiency >125%, defying conventional limits.
Step-by-step: (1) Nanotip induces fringing fields; (2) Enhances local E-field in FE; (3) Couples to channel via reduced C-ratio; (4) Switches polarization at low V; (5) Yields hysteresis in I-V curves.
Expert Praise and Industry Ramifications
Science Advances reviewers hailed: “These nano-gate ferroelectric transistor devices exhibit excellent memory performance, and the physical mechanism... holds significant implications for memory development.” Qiu emphasizes energy savings: “one-tenth of the lowest reported internationally.”
For China, this bolsters domestic AI chip leadership, reducing reliance on imports. Globally, it challenges silicon giants, spurring R&D in ferroelectric tech. Check academic CV tips for semiconductor roles.
Photo by Jason Leung on Unsplash
Future Outlook: Sub-1-nm Era and Beyond
Universal for HfO2, the nanogate paves 3D stacking for terabit densities. Applications span AI accelerators to quantum-inspired computing. PKU plans prototypes; mass production viable with CMOS flows. As Qiu states: “Strong potential for sub-1-nm chips.”
Stakeholders: Chipmakers gain low-power edges; AI firms efficiency; academics new paradigms. Challenges: Yield at scale, integration. Solutions: PKU's IP roadmap.
Discover higher ed jobs, rate professors, or career advice in this dynamic field. For China-focused roles, visit AcademicJobs China.
