Rate My Professor Abhijit Das

Abhijit Das serves as an Assistant Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology Hyderabad, having joined on October 6, 2025. He obtained his Ph.D. from the Indian Institute of Technology Guwahati, where his dissertation earned the Best PhD Thesis Award during the 24th convocation in June 2022. Earlier in his career, Das worked as a Senior Silicon Design Engineer at AMD on the performance modeling team for the Zen microarchitecture, a Postdoctoral Researcher at the TARAN group at INRIA, and Director of Research and Group Leader at N3Cat, Universitat Politècnica de Catalunya BarcelonaTech. His academic journey was supported by GATE Fellowships from the Ministry of Education, Government of India, for his M.Tech. (2013-2015) and Ph.D. (2015-2020), as well as NEC Scholarships for his B.Tech. (2010-2013) and Diploma (2007-2010).

Das's research focuses on computer architecture, systems for AI/ML, and quantum computing systems, particularly optimizing data movement to improve performance, efficiency, and security. Notable publications include "SECTAR: Secure NoC using trojan aware routing" presented at the 14th IEEE/ACM International Symposium on Networks-on-Chip in 2020 (53 citations), "Chip and package-scale interconnects for general-purpose, domain-specific, and quantum computing systems—Overview, challenges, and opportunities" in IEEE Journal on Emerging and Selected Topics in Circuits and Systems in 2024 (38 citations), "Multi-objective hardware-mapping co-optimisation for multi-dnn workloads on chiplet-based accelerators" in IEEE Transactions on Computers in 2024 (28 citations), and "Critical packet prioritisation by slack-aware re-routing in on-chip networks" at the Twelfth IEEE/ACM International Symposium on Networks-on-Chip in 2018 (15 citations). He leads the EWiC project, funded by an ERC Proof of Concept grant of €150,000 from 2024 to 2026, aimed at emulating wireless communication among chiplets in computing systems. Das has garnered awards such as Best Associate Editor in IEEE CASS 2024 (July 2025), Best Student Paper Award at ISVLSI 2022, Qualcomm Innovation Fellowship Finalist 2019, and Best Poster Awards at various conferences. He serves on program committees including ESWEEK 2026 (Industry Engagement Co-Chair), DATE 2026, HiPC 2025, and artifact evaluation for ISCA 2025 and ASPLOS 2025. Additionally, he has created widely viewed gem5 tutorials (over 35,000 YouTube views) and the CA Deadlines website.