The Dawn of Quantum-Resistant Hardware in Singapore

Singapore's higher education landscape is once again at the forefront of global technological innovation, with TUMCREATE, a research powerhouse established by the Technical University of Munich (TUM) in collaboration with Singapore's National Research Foundation (NRF), taking the lead in developing the world's first fully open-source post-quantum cryptography (PQC)-secure 64-bit RISC-V processor. This groundbreaking initiative, part of the QUASAR-CREATE program, brings together Nanyang Technological University (NTU Singapore) and the National University of Singapore (NUS), underscoring the city-state's commitment to securing future digital infrastructures against the looming threats posed by quantum computing.

Post-quantum cryptography refers to cryptographic algorithms designed to be secure against attacks from quantum computers, which could potentially break widely used public-key systems like RSA and elliptic curve cryptography (ECC) using algorithms such as Shor's. RISC-V, on the other hand, is an open-standard instruction set architecture (ISA) that allows for customizable, royalty-free processor designs, making it ideal for embedding specialized security features. By combining these, the project aims to create a verifiable, transparent hardware platform that can withstand both classical and quantum threats.

This collaboration not only advances research but also positions Singapore's universities as key players in the global race toward quantum-safe technologies, fostering interdisciplinary expertise in electrical engineering, computer science, and cybersecurity.

Unpacking the QUASAR-CREATE Initiative

The QUASAR-CREATE program, a 3.5-year effort launched under Singapore's Research, Innovation, and Enterprise 2025 (RIE2025) and extending into RIE2030 frameworks, is funded by the NRF and focuses on quantum security and resilience for emerging technologies. QUASAR stands for Quantum Security and Resilience for Emerging Technologies, integrating post-quantum cryptography (PQC) with quantum key distribution (QKD) to build robust systems.

TUMCREATE leads Thrust 1: Secure Hardware Platform, developing an open-source RISC-V-based chip enriched with PQC accelerators. The processor incorporates hardware-level protections against side-channel attacks (like timing or power analysis) and physical tampering, alongside a secure operating system and trusted execution environments. Fabrication will utilize GlobalFoundries' 180nm process in Singapore, ensuring local production capabilities.

• PQC Accelerators: Hardware units optimized for NIST-standardized algorithms like CRYSTALS-Kyber for key encapsulation and CRYSTALS-Dilithium for signatures.
• Design Tools: Fully open-source flow for design space exploration and backend synthesis.
• Verification: Functional testing and side-channel resistance validation.

Practical demonstrators include FIDO2-compliant authentication tokens for passwordless login, with extensibility to QKD for hybrid classical-quantum security.

Roles of Singapore's Leading Universities

NTU Singapore's School of Electrical and Electronic Engineering (EEE) plays a pivotal role in RISC-V platform development and QUASAR professorship, funded by the Dieter Schwarz Foundation. NTU's expertise in quantum cybersecurity complements the hardware focus, building on its QUASAR program launched in 2024 to counter quantum threats.

NUS contributes through its deep involvement in Singapore's quantum ecosystem, including the Centre for Quantum Technologies (CQT), a national research center hosted at NUS with participation from NTU and Singapore University of Technology and Design (SUTD). CQT's work in quantum information science provides foundational knowledge for PQC integration.

TUMCREATE, as a unique higher education outpost, bridges European and Singaporean research, leveraging TUM's semiconductor design prowess. This trilateral effort exemplifies how Singaporean universities are pooling resources for national priorities.

The Technical Deep Dive: Building Quantum-Resistant Hardware

Developing a PQC-secure RISC-V processor involves several steps. First, selecting RISC-V core (e.g., 64-bit RV64IMAFDC) and extending it with custom accelerators. Step 1: Implement lattice-based PQC primitives in hardware for efficiency—software alone is too slow for constrained devices. Step 2: Integrate side-channel countermeasures like masking and constant-time execution. Step 3: Develop a secure bootloader and OS (e.g., based on seL4 microkernel) with root-of-trust. Step 4: Open-source the entire RTL (register-transfer level) design using tools like Chisel or SpinalHDL, with verification via formal methods.

The 180nm process balances cost, performance, and security for prototypes. Performance targets include sub-millisecond key exchange, crucial for IoT and edge devices. This contrasts with proprietary chips like ARM, emphasizing Singapore's push for technological sovereignty.Learn more about RISC-V's role in secure systems.

Singapore's Quantum Research Ecosystem in Higher Education

Singapore invests heavily in quantum tech, with RIE2030 allocating billions for semiconductors and quantum. CQT, operational since 2007, has produced over 1,000 researchers trained in quantum info. NTU's quantum-safe cybersecurity program and NUS's quantum engineering initiatives complement QUASAR.

Recent collaborations like OCBC with NTU, NUS, SMU for quantum research highlight industry ties. GlobalFoundries' Fab 7 in Woodlands supports local chip production. This ecosystem trains PhDs and postdocs, with QUASAR creating jobs in hardware security.Explore CQT's contributions.

Implications for Singapore's Higher Education and Careers

For universities, QUASAR boosts research output, attracting talent. NTU and NUS students gain hands-on experience in cutting-edge hardware design, vital for Singapore's Smart Nation initiative. Job postings for PhDs/postdocs in PQC hardware signal growing demand—skills in Verilog, side-channel analysis, RISC-V extension are hot.

Careers in quantum security offer high prospects: median salaries for chip designers exceed SGD 100k, with roles at IMDA, A*STAR, global semis. This aligns with Singapore's goal of 20,000 quantum-skilled workers by 2030.

Expert Perspectives and Quotes

Prof. Ulf Schlichtmann, TUMCREATE CEO: “QUASAR-CREATE contributes to embedding security at hardware level, supporting secure chip technologies.” Prof. Georg Sigl: “Post-quantum security needs hardware anchoring; we're building open-source RISC-V chip.” NTU Prof. Gwee Bah Hwee: “Proactively addressing quantum challenges supports Singapore’s secure tech adoption.”

These voices highlight the project's strategic importance.

Challenges and Solutions in Post-Quantum Transition

Challenges: PQC algorithms are larger/slower; hardware optimization key. Solutions: Custom accelerators reduce latency. Singapore's approach—open-source—enables global scrutiny, unlike closed vendors. Timeline: Prototypes 2027, full chip by program end 2029.

Photo by Logan Voss on Unsplash

• Risks: Side-channel leaks in PQC impl.
• Mitigations: Masking, shuffling.
• Comparisons: Vs ARM TrustZone—more customizable.

Future Outlook: Quantum-Safe Singapore

QUASAR positions Singapore as quantum security leader, influencing ASEAN via NQSN+. For higher ed, more interdisciplinary programs expected. Actionable: Students pursue RISC-V/PQC courses at NTU/NUS; faculty collaborate via CQT.

This project exemplifies how Singaporean universities drive national innovation, securing a quantum-resilient future.