Rate My Professor Joseph Cavallaro

Cavallaro's research centers on special-purpose VLSI processor architectures for signal processing, wireless communications, computer graphics, and robotics, emphasizing matrix computations on parallel arrays and numerical algorithms mapped to low-power DSP, ASIC, and ASIP platforms. He has led projects such as BRICK for scalable massive MIMO base stations using decentralized baseband processing and antenna clustering on FPGA and GPGPU clusters; the Wireless LAN and MIMO FPGA Testbed for reconfigurable architectures in the 2.4 GHz ISM band; VLSI enhancements for real-time wireless algorithms; and the Gnomes Sensor Network Testbed for low-power remote structural monitoring. His achievements include election as IEEE Fellow in 2015 for contributions to VLSI architectures and algorithms for signal processing and wireless communications, the IEEE Circuits and Systems Society Distinguished Lecturer award for 2012-2013, NSF Research Initiation Award from 1989-1992, and multiple best paper awards including IEEE Great Lakes Symposium on VLSI (2009), IEEE International SoC Conference (2008), and IEEE Workshop on Signal Processing Systems (2008). Key publications encompass "Large-scale MIMO detection for 3GPP LTE: Algorithms and FPGA implementations" (IEEE Journal of Selected Topics in Signal Processing, 2014), "Decentralized Baseband Processing for Massive MU-MIMO Systems" (IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2017), "CORDIC Arithmetic for an SVD Processor" (Journal of Parallel and Distributed Computing, 1988), "A Flexible LDPC/Turbo Decoder Architecture" (Journal of Signal Processing Systems, 2011), and "Robotic Fault Detection and Fault Tolerance: A Survey" (Reliability Engineering & System Safety, 1994). Cavallaro has served as Associate Editor for IEEE Transactions on Signal Processing (2013-2017), IEEE Signal Processing Letters (2013-2017), and Springer Journal of Signal Processing Systems.