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5.05/4/2026

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About P

Dr. P. Nagarajan serves as Associate Professor in the Department of Electronics and Communication Engineering at SRM Institute of Science and Technology, Vadapalani Campus. He earned his B.E. in Electronics and Communication Engineering from Anna University, Chennai, in May 2007, securing Academic Topper awards, an M.E. in Applied Electronics from the same university in June 2009 as a university rank holder, and a Ph.D. in VLSI Design with a focus on advanced communication systems applications from Anna University in March 2015.

His academic career, spanning over 17 years, began as a Teaching Assistant at RVS College of Engineering and Technology, Dindigul, from May 2007 to May 2009. He then served as Lecturer and Assistant Professor at PSNA College of Engineering and Technology, Dindigul, until February 2016, followed by Associate Professor roles at VEL Tech University, Chennai, from February 2016 to July 2017, and Sree Vidyanikethan Engineering College, Tirupati, from July 2017 to October 2020. From October 2020 to January 2023, he was Professor at Rajalakshmi Institute of Technology, Chennai, prior to his current appointment at SRMIST. Dr. Nagarajan's research specializations include VLSI Design, Mixed-signal VLSI Design, Digital Signal Processing, Signals and Systems, Electromagnetic Fields and Compatibility, Transmission Lines and Waveguides, Mobile and Wireless Communication, Electronic Devices and Circuits, ASIC Design, CMOS VLSI Design, CAD VLSI, Testing of VLSI Circuits, and Image and Signal Processing using FPGA implementation for biomedical and hyperspectral images. His key publications encompass 'Design and Simulation of a Novel 16T SRAM Cell for Low Power Memory Architecture' in Journal of Circuits, Systems and Computers (2023), 'Cancer Detection Using Multi-layered Kretschmann Configuration-based Refractive Index Sensor' in Plasmonics (2024), 'Design and Analysis of a Plasmonic Metasurface-Based Graphene Sensor for Highly Sensitive and Label-Free Detection of COVID-19 Biomarkers' in Plasmonics (2024), 'Design of implicit pulsed – dual edge triggering flip flop for low power and high speed clocking systems' in International Journal of Wavelets, Multiresolution and Information Processing (2019), and numerous IEEE conference papers on low-power VLSI components and signal processing (2022-2024).