The Groundbreaking Review on Cu-Cu Hybrid Bonding

Copper-to-copper (Cu-Cu) hybrid bonding represents a pivotal advancement in three-dimensional integrated circuit (3D IC) technology, enabling unprecedented levels of interconnect density and performance. A newly published review paper, titled "Cu–Cu hybrid bonding technology: from physical mechanisms to system integration for 3D ICs," provides a comprehensive roadmap from fundamental mechanisms to practical implementation. Authored by B. Jiang and colleagues, this 2025 publication in Moore and More dissects how this technology overcomes traditional packaging limitations, such as pitch sizes exceeding 10 micrometers and high bonding temperatures that risk device damage.

The review arrives at a critical juncture for the semiconductor industry, where demands from artificial intelligence (AI) accelerators, high-bandwidth memory (HBM), and chiplet architectures are pushing beyond conventional interconnects. Cu-Cu hybrid bonding achieves sub-micrometer pitches, drastically reducing parasitic capacitance and resistance while improving thermal conductivity. This positions it as essential for next-generation high-performance computing (HPC) and heterogeneous integration.

In Singapore, a global semiconductor powerhouse, this review resonates deeply with ongoing research at institutions like Nanyang Technological University (NTU) and the A*STAR Institute of Microelectronics (IME). These efforts align with the nation's push toward advanced packaging, supporting companies like GlobalFoundries and Micron.

Fundamentals of Cu-Cu Hybrid Bonding Technology

Hybrid bonding combines dielectric-to-dielectric and metal-to-metal (Cu-Cu) connections in a seamless, bump-less process. Unlike flip-chip or through-silicon via (TSV) methods, it forms direct bonds at the wafer or die level, eliminating solder bumps for finer pitches below 1 micrometer. The process typically involves chemical mechanical polishing (CMP) to achieve ultra-flat surfaces (<1 nm roughness), plasma activation for hydrophilic bonding, and annealing under pressure.

Two primary pathways dominate: dielectric bond interface (DBI) and surface-activated bonding (SAB). DBI leverages room-temperature oxide bonding via silanol (Si-OH) groups forming hydrogen bonds, followed by annealing to create covalent Si-O-Si networks. SAB uses argon ion bombardment to remove native oxides, enabling low-temperature (<200°C) metallic diffusion. The review details how these yield bonding strengths exceeding 200 MPa, far surpassing wire bonding's 100 MPa limit.

Singapore's IME has pioneered low-temperature variants, crucial for heat-sensitive devices like advanced logic and memory stacks. NTU researchers have demonstrated wafer-level fine-pitch Cu-Cu bonding, vital for scaling 3D ICs.

Physical Mechanisms Driving Cu-Cu Bonds

At the core, Cu-Cu bonding relies on solid-state atomic diffusion facilitated by thermal expansion and creep deformation. Under heat (200–400°C) and pressure, copper atoms migrate from high-stress regions to voids, achieving near-100% bonding fraction (BF). The review provides equations modeling this: elastic strain ε = σ/Y (σ stress, Y modulus), strained volume V ≈ π(1-r²)l²Δh (r void radius, l length, Δh height), and BF = 1 - r' where r' is residual void radius.

Nanotwinned Cu enhances this with (111) crystallographic orientation, reducing required temperature to <250°C and boosting electromigration resistance. Dielectric mechanisms involve viscoelastic flow above 800°C, but plasma activation lowers this threshold by 50–70%.

• Hydrophilic bonding stages: Van der Waals → H-bonding → covalent Si-O-Si.
• Creep: Stress-driven grain boundary diffusion fills voids exponentially.
• CTE mismatch (Cu 17 ppm/K vs. SiO₂ 0.5 ppm/K) induces radial expansion for intimate contact.

These insights guide Singapore researchers at IME, where passivation layers like Ag and Ru suppress oxidation for reliable low-temp bonds.

Overcoming Key Challenges in Hybrid Bonding

Despite promise, challenges persist: interfacial delamination from thermal mismatch, electromigration in fine pitches, and warpage from CTE differences. TSV-induced stresses exceed 80 MPa shear, degrading mean time to failure (MTTF) by 30–50%. Process complexity demands atomic-level flatness; contamination or misalignment drops yield below 90%.

Solutions include nanotwinned Cu for creep enhancement, passivation (e.g., Pd nano-seeds accelerate diffusion), and optimized CMP (three-step: abrasive slurry, barrier removal, buffing for <2.5 μm pitch). Low-temp annealing (150–200°C, 1–2 hours) achieves >90% yield. The review stresses dielectric selection (SiCN over SiO₂ for better matching).

In Singapore, NTU's work on plasma-activated bonding addresses these, enabling heterogeneous stacks without thermal damage.

Process Breakthroughs Enabling Scalability

CMP is pivotal: multi-step processes ensure pad dishing <5 nm and roughness RMS <0.5 nm. Table parameters: pH 10 slurry, 1.5 psi pressure, 60 rpm speed yield 95% planarity. Passivation breakthroughs—Ag layers form fine grains (<100 nm), aiding diffusion at 200°C.

Annealing optimizations: ramp rates 5–10°C/min, holds at 250°C for 2 hours. ECD (electro-chemical deposition) uniformity <5% variation across 300 mm wafers. These push pitches to 1 μm, with 80% capacitance reduction vs. micro-bumps.

• Three-step CMP: Removes Cu over-burden, barrier/Cu, final polish.
• Passivation options: Ru (oxidation resistant), Ti (adhesion promoter).
• Yield metrics: >90% bonded area post-anneal.

A*STAR IME prototypes these for industry, collaborating with Applied Materials on heterogeneous packaging.

Strategies for 3D IC System Integration

Integration fuses HB with TSV/μTSV for multi-layer stacks. DBI flows: align → room-temp dielectric bond → anneal Cu-Cu. For heterogeneous (e.g., GaN/Si), co-optimized CMOS/HEMT yields 20% power gain, 30% thermal drop. Wafer-to-wafer (W2W) suits HBM; die-to-wafer (D2W) for logic-memory.

Examples: AMD MI300 (HBM3 via HB, >5 TBps); Sony IMX260 (TSV-free CIS). Roadmap shows <10 μm pitch by 2025, sub-1 μm by 2030. Read the full review here.

Singapore's ecosystem—IME's 200mm SiC line, NTU's fine-pitch demos—positions it for leadership.

Transformative Applications in High-Performance Systems

HBM3 (Samsung): 12 layers, 819 GB/s bandwidth, 35% power save via HB. CMOS sensors: Sony's stacked pixels boost sensitivity 2x, density 4x. Heterogeneous: InP HBT/Si for mm-wave (low loss). Future: AI chips, power ICs with wide-bandgap semis.

Singapore leverages this via IME's advanced packaging center, prototyping for HPC/AI amid $800M RIE2030 funding.

Singapore's Vanguard Role in Hybrid Bonding Research

Singapore invests heavily in semiconductors ($20B ecosystem). A*STAR IME leads heterogeneous integration, with hybrid bonding pilots for AI era. Collaborations: Nearfield Instruments (metrology), Applied Materials (tools). NTU's theses on low-temp Cu-Cu enable 3D stacking without warpage.

NUS materials labs contribute nanotwinned Cu studies. These align with national goals: 3D packaging hub by 2030. IME's advanced packaging research.

Implications for Singapore's Higher Education and Careers

NTU/IME programs train experts in HB, with research fellows advancing low-temp processes. Careers boom: semiconductor jobs up 20%, roles in packaging R&D. Unis partner industry (GlobalFoundries) for internships.

Review inspires curricula: microelectronics courses integrate HB modules. Future: PhD opportunities in 3D ICs, fueling Singapore's $100B chip ambition.

Photo by Daniele Levis Pelusi on Unsplash

Future Outlook: Scaling Hybrid Bonding Globally

Prospects: Sub-500 nm pitches, room-temp bonds via novel passivations. Challenges: Cost/yield for volume. Singapore poised via IME/NTU, exporting tech worldwide. Actionable: Invest in CMP tools, talent pipelines.

This review cements HB's role in Moore's Law extension, with Singapore at forefront.