ASIC Test Chip Physical Design Architect

We are seeking a motivated engineer with experience in ASIC architecture to join our team for defining and delivering test chips for new technology pathfinding. You will be involved in the definition and design of demonstrator test chips focused on next-generation memory technologies. You will interact with device, integration, and system/DTCO teams to drive projects from concept to silicon tape-out in close collaboration with different teams (device, integration, analog design, test, etc.).

What you will do

• Test chip demonstrator definition, specifications, and planning.
• Physical design integration (including floorplanning) and signoff coordination at sub-system and full chip level.
• RTL design, IP selection and integration.
• Definition of the strategy for verification, measurement and characterization, including test access structures (DFT, BIST, ...) and agreements with test team.

What we do for you

A full-time position in imec Leuven, Belgium or imec Cambridge, UK. An exciting position in a rapidly growing, multi-disciplinary team. The chance to interact closely with circuit designers, device experts and process integration engineers. High impact and visibility through publications and interactions with imec’s major foundry, fabless and EDA partners.

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.

We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.

Who you are

The ideal candidate will have a Master degree in Electronics with at least 5 years relevant industrial or academic experience in circuit design. You have a digital circuit design and top-level physical implementation background. You have experience in test chip or demonstrator definition and tape-out leadership. You have an understanding of the basic functioning and characteristics of emerging memories. You have a good understanding of on-chip partitioning, clocking, and design-for-test structures. You are proficient with either Cadence/Synopsis EDA tools and flows. You are acquainted with measurement equipment interfaces and can understand their limitations and take those into account in your design for test strategy. Experience with either PCB, demo board design or FPGA programming is a plus. Experience with automatic, semi-automatic probe-stations or manual probe measurement and notions on probe pad layouts and probecard design is a plus. You have worked in multi-disciplinary teams, ideally both interacting with hardware designers as well as EDA vendors and foundry partners. You have a critical mindset, eager to explore new challenges in the future and evolve together with the changing R&D demands. You are an open and constructive team player. Team lead experience is a plus.

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Job details

Title: ASIC Test Chip Physical Design Architect

Employer: imec

Location: Kapeldreef 75 Leuven, Belgium; Hills Road Cambridge, CB2 0AH Cambridge, United Kingdom

Published: 2025-09-01

Application deadline: Unspecified

Job type: Engineer

Field: Electronics, Systems Engineering, Programming Languages