The position will focus on the design, implementation, and evaluation of new communication protocols and systems for distributed computation across accelerators. Research may span hardware/software co-design, high-performance networking, accelerator communication, and next-generation server interconnects.

The successful candidate will conduct research on high-performance communication and interconnect systems, with particular emphasis on protocols and mechanisms for communication among CPUs, GPUs, and other hardware accelerators.

Qualifications:

An ideal candidate will have:

• A Ph.D. in Computer Science, Computer Engineering, Electrical Engineering, or a closely related field, completed by the start date.
• Strong systems programming experience in CUDA, C/C++, and RTL.
• Significant experience with high-performance server and accelerator interconnect technologies and protocols, including technologies such as:
  • PCI Express (PCIe)
  • Compute Express Link (CXL)
  • RDMA
  • GPUDirect
  • Enso
• Experience with Internet and transport protocols, including TCP/IP.
• A strong research background in computer systems, networking, computer architecture, distributed systems, or related areas.