Researcher in 3D Emerging Memories (DRAM/Ferro/IGZO 2T0C)

Memory design and technology exploration for 3D scaled technologies.

What you will do

In this position, you will join the imec PACTS department (Pathfinding Co-Optimization Technology and Systems), in the Technology Enablement through Circuit Assessment (TECA) team, from imec UK in Cambridge, or imec Leuven, in Belgium. You will join the memory pathfinding activities, and focus on the most advanced dense 3D memories, including 3DDRAM, IGZO-based DRAM, and Ferro-based memories (FeFETs, FeCaps). Your role will involve investigating these emerging memory solutions, bridging technology to systems by exploring bitcell/array and periphery implications, and innovating with technology/circuit solutions. You will collaborate on the design of relevant testchips and technology demonstrators for these emerging memories.

This includes:

• You will use your knowledge of circuit design implementation to investigate memory bitcell, array, macro and periphery IC layout and automation, and assess power, performance, and area of various memory technology options.
• Innovate on array structures, periphery architectures, 3D-solutions for denser and more optimal memories.
• Understand and advance the memory roadmap benchmarking these new technologies to relevant references.
• Define relevant test structures, performing circuit simulations and layout, developing measurement and characterization strategies, and ensuring all necessary layout qualifications (DRC, LVS, PEX) for test chips tape-outs.
• You will need to interact with the test chip architect, technology teams, and System/Design-Technology Co-Optimization (STCO/DTCO) teams to drive the test chip to success.
• You will help enable imec PDKs for most advanced process technologies for memory and drive towards industry standard methods and ease of use.

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow. 
We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.  
We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.

• A full-time position in Cambridge, UK, or Leuven, Belgium.
• An exciting position in a rapidly growing, multi-disciplinary team.
• The chance to interact closely with circuit designers, device experts and process integration engineers.
• High impact and visibility through potential publications and interactions with major foundry, fabless and EDA partners in imec’s eco-system.

Who you are

• The ideal candidate will have a PhD or master degree in Electronics with at least 5 years relevant industrial or academic experience in DRAM (or similar) memory circuit design.
• You have a mixed-signal (AMS) design background and brought your circuit design to hardware.
• Ideally, you would have experience in relevant analog circuitry: charge pump design, ADCs...
• You are fully acquainted with circuit design tools, including layout and circuit simulation (Virtuoso IC design, Hspice, Calibre DRC/LVS,…)
• You have worked in multi-disciplinary teams, ideally interacting both with hardware designers as well as EDA vendors and foundry partners.
• You have a critical mindset, eager to explore new challenges in the future and evolve together with changing R&D demands .
• You have habits in automation, versioning, documenting.
• You are an open and constructive team player.