Minimum qualifications: Bachelor's degree in electrical engineering or equivalent practical experience 2 years of experience in SoC Pre-Silicon power estimation/analysis/optimization
Experience with low power design techniques Preferred qualifications: Strong understanding of SoC Architecture, memory hierarchy, coherency, fabric interconnect protocols, clocking and power management Experience with System Verilog Experience with scripting languages (e.g., Python, Perl) Excellent problem-solving and analytical skills About the Job Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users. With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Drive pre-silicon power estimation and analysis using power estimation tools both at RTL and Netlist level Develop methodologies around power estimation tools and incorporate best practices to improve the power estimation fidelity Run and estimate the power consumption of the IP and Sub System Analyze power estimation reports to identify power-saving opportunities and influence both the physical design aspect and the u-arch design aspects of the design for power reduction
