Rate My Professor Caroline Trippel

Trippel's research centers on computer architecture, promoting high assurance—correctness, security, and reliability—as primary design goals through formal methods and automated reasoning techniques for hardware systems. Her contributions include formal analysis influencing the RISC-V ISA memory consistency model via participation in the RISC-V Memory Model Task Group, prompting Intel to update its Software Security Guidance based on the Serberus Spectre defense developed in her lab, and tools that synthesized new variants of Meltdown and Spectre attacks. Notable publications encompass "Serberus: Protecting Cryptographic Code from Spectres at Compile-Time" (IEEE S&P, 2024), "RTL2MμPATH: Multi-μPATH Synthesis with Applications to Hardware Security Verification" (MICRO, 2024), "CounterPoint: Using Hardware Event Counters to Refute and Refine Microarchitectural Assumptions" (ASPLOS, 2026, Best Paper Award), "CheckMate: Automated Exploit Program Generation for Hardware Security Verification" (MICRO, 2018, IEEE Top Pick), and "TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA" (ASPLOS, 2017, IEEE Top Pick). Awards include the 2026 Sloan Research Fellowship, NSF CAREER Award (2023), 2025 Google ML and Systems Junior Faculty Award, 2024 Intel Rising Star Award, 2023 Intel Outstanding Researcher Award, and 2020 ACM SIGARCH/IEEE TCCA Outstanding Dissertation Award. She has given invited keynotes at POPL 2026 and CAV 2023 and serves on program committees for conferences such as ISCA and HPCA.