Ultra-Low-Power Digital ASIC Design for Next-Generation Implantable Brain-Computer Interfaces

About the Project

Supervisory team: Dr. Majid Zamani

Implantable BCIs are limited by a strict power budget to prevent thermal tissue damage. Wireless data transmission consumes most power, especially as channel counts scale. This project focuses on designing ultra-low-power ASICs that perform on-chip neural processing, drastically reducing bandwidth needs while maintaining decoding accuracy.

Implantable Brain-Computer Interfaces (BCIs) hold the promise of restoring communication and mobility for individuals with paralysis, as well as enabling new therapeutic avenues for neurological disorders. However, the clinical translation of high-performance BCIs is fundamentally limited by one critical constraint: power consumption.

State-of-the-art implantable BCIs with high-channel-count microelectrode arrays generate massive amounts of neural data, hundreds of megabits per second, yet must operate within a strict power budget of tens of milliwatts to prevent tissue damage from heat dissipation. Wireless data transmission, the dominant power consumer in current systems, creates a fundamental bottleneck. The solution lies not in transmitting raw data, but in intelligent, on-chip processing.

This project focuses on the design of ultra-low-power digital Application-Specific Integrated Circuits (ASICs) that embed intelligence directly at the neural interface. You will develop custom silicon architectures that perform on-chip neural signal processing, feature extraction, and inference, radically reducing wireless bandwidth requirements while maintaining high decoding accuracy.

Implantable BCIs face a fundamental physical bottleneck: thermal dissipation. The human body tolerates only minimal temperature rise in neural tissue (typically < 1–2°C above body temperature), which limits implantable electronics to a power budget of approximately 10–50 milliwatts for a high-channel-count system. Within this tight constraint, wireless telemetry, the transmission of raw neural data through the skin, can consume 80–90% of the total power. As channel counts scale toward 1,000+ electrodes to achieve higher decoding accuracy, this problem becomes exponentially worse. Simply improving battery life or wireless protocols is insufficient; the solution requires a fundamental architectural shift.

Entry requirements

You must have a UK 2:1 honours degree or its international equivalent.

Fees and funding

We offer a range of funding opportunities for both UK and international students. Horizon Europe fee waivers automatically cover the difference between overseas and UK fees for qualifying students.

Competition-based Presidential Bursaries from the University cover the difference between overseas and UK fees for top-ranked applicants.

Competition-based studentships offered by our schools typically cover UK-level tuition fees and a stipend for living costs for top-ranked applicants.

Funding will be awarded on a rolling basis, so apply early for the best opportunity to be considered.

For more information, please visit our postgraduate research funding pages.

How to apply

Apply now

You need to:

• choose programme type (Research), 2026/27, Faculty of Engineering and Physical Sciences
• select Full time or Part time
• search for programme PhD Electronic & Electrical Engineering (7092)
• add name of the supervisor in section 2 of the application

Applications should include:

• research proposal describing how you would tackle this problem
• one-page statement outlining suitability for the project
• Two pages CV (resumé), including GPA and publications
• 2 academic references
• degree transcripts and certificates to date
• English language qualification (if applicable)

Contact us

Faculty of Engineering and Physical Sciences

If you have a general question, feps-pgr-apply@soton.ac.uk.

Project leader

For an initial conversation, M.Zamani@soton.ac.uk.