"Process Engineer x2 (744352)"

The Process Engineer will be responsible for the day-to-day execution and optimisation of semiconductor packaging processes, contributing to the delivery of high-impact industrial research, prototyping and scale-up projects and programmes.

FTE: 1 (35 hours/week)
Term: Open-ended

The University has been successful in attracting capital support for the establishment of the National Advanced Semiconductor Packaging and Integration Centre (NASPIC), based within our new facility close to Glasgow Airport. The line is one of a kind as it has been designed to allow for a broad range of present and future devices. Its open access governance model is unique in Europe and very rare elsewhere. NASPIC will explore and develop disruptive packaging and integration technologies to make next-generation systems at lower cost and with more energy and packaging efficiency.

NMIS is seeking to appoint a motivated and skilled Process Engineer to support advanced semiconductor packaging and integration activities, with a focus on process manufacturing, assembly, and reliability for power electronics, photonics and advanced CMOS applications. As a key member of the engineering team, you will work under the guidance of the Principal Engineer and Senior Packaging Engineer to deliver high-quality process development, prototyping and scale-up projects. You will play a vital role in establishing robust back-end processes, ensuring technical excellence and supporting the transition of packaging technologies from lab-scale innovation to pilot production.

Informal enquiries about the post can be directed to Graham Nicholson, Laboratory Manager (graham.nicholson@strath.ac.uk).

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