Job Information
Organisation/Company: University College Dublin
- Research Field: Engineering » Electrical engineering
- Researcher Profile: First Stage Researcher (R1)
- Application Deadline: 2 Sep 2026 - 10:26 (UTC)
- Country: Ireland
- Type of Contract: Temporary
- Job Status: Full-time
- Is the job funded through the EU Research Framework Programme?: Not funded by a EU programme
Offer Description
Applications are invited for a temporary post of a RF/mmWave IC Design Engineer within UCD School of Electrical and Electronic Engineering.
This engineering role exists to execute the circuit design, full-custom layout, and block-level integration of critical sub-systems for a next-generation sub-THz transceiver SoC. Operating within NovaUCD's deep-tech commercialization framework, the appointee translates specific development milestones into verified silicon components. The position serves as a core technical contributor, collaborating closely across cross-functional RF, analog, digital, and validation teams to ensure chip-level design synchronization.
Reporting to the Principal Investigator, the successful candidate maintains primary technical accountability for block-level circuit implementation and full-custom layout development. Key responsibilities include managing parasitic mitigation, executing electromagnetic modeling, and driving block-level physical verification. The primary expected outcome is the successful delivery of production-ready sub-THz transceiver components that form a verified, reliable baseline for commercial technology translation.
The mmWave TRx project, funded under an Enterprise Ireland Commercialisation Fund programme, is focused on the development of a highly integrated sub-THz transceiver SoC for next-generation communication and sensing applications. The project combines cutting-edge RFIC design, antenna integration, and silicon validation, with the definitive objective of creating robust technology suitable for a future venture-backed spin-out company.
Salary Range: €55,000 - €70,000 Per Annum
Appointment on the above range will be dependent upon qualifications and experience.
Closing date: 12:00 noon (local Irish time) on 02 September 2026.
Applications must be submitted by the closing date and time specified. Any applications which are still in progress at the closing time of 12:00 noon (Local Irish Time) on the specified closing date will be cancelled automatically by the system. UCD are unable to accept late applications.
UCD do not require assistance from Recruitment Agencies. Any CV's submitted by Recruitment Agencies will be returned.
Prior to application, further information (including application procedure) should be obtained from the Work at UCD website: https://www.ucd.ie/workatucd/jobs/
Where to apply
Website: https://www.aplitrak.com/?adid=eWFzZW1pbi5vemRlbWlyLjMyMjQ1Ljk5MDhAdW5pY2R1Ymxpbi5hcGxpdHJhay5jb20
Requirements
Research Field: Engineering
Education Level: PhD or equivalent
Research Field: Engineering
Education Level: Master Degree or equivalent
Skills/Qualifications
RF, mmWave Circuit Design Principles, Full-Custom Block Layout & Multi-Block Chip Integration, Parasitic-Aware Simulation & Post-Layout Extraction (PEX), Electromagnetic (EM) Modeling & Passive Optimization, Cadence Virtuoso Environment
Additional Information
Eligibility criteria
Mandatory:
- MSc or PhD in RF / Microwave / mmWave IC Design, Microelectronics, or a related discipline.
- 2-5 years of relevant industrial or advanced research track record.
- Solid experience with Cadence Virtuoso (Layout XL/GXL) and SpectreRF.
- Strong understanding of RF/mmWave circuit design principles and high-frequency layout considerations.
- Familiarity with post-layout verification, parasitic extraction (PEX), and design sign-off flows.
- Clear understanding of physical IC design constraints (parasitics, device matching, symmetry, shielding).
- Strong layout and test knowledge and experience are key to this position.
- Design and capture schematics for RF/mmWave circuit building blocks.
- Perform thorough circuit simulations and design optimization across PVT corners.
- Execute full-custom layout blocks in Cadence Virtuoso, utilizing layout matching and parasitic minimization techniques.
- Run full post-layout extractions, checks, and simulations to verify circuit performance constraints.
- Support top-level integration, physical verification flows, and design documentation for tape-out readiness.
- Assist the lab validation team during silicon bring-up, measurement, and troubleshooting phases.
- Demonstrate a strong capacity to collaborate effectively and communicate technical findings clearly within multidisciplinary engineering teams.
- Candidates must demonstrate an awareness of the equality, diversity, and inclusion agenda.
Desirable:
- Hands-on experience with EM simulation tools (e.g., HFSS, EMX, Momentum).
- Experience with physical verification suites (Calibre, Assura, PVS, or Pegasus).
- Experience with RF laboratory measurement instruments and silicon validation setups.
- Familiarity with advanced deep sub-micron nodes, CMOS, or FD-SOI technologies.
- Exposure to mixed-signal configurations or digitally-assisted RF calibration architectures.
Selection process
https://www.ucd.ie/workatucd/jobs/
Website for additional job details: https://www.ucd.ie/
Work Location(s)
Number of offers available: 1
Company/Institute: University College Dublin
Country: Ireland
City: Dublin
Contact
Website: https://www.ucd.ie/
E-Mail: yasemin.ozdemir@ucd.ie
Phone
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